# UVM Tutorial for Candy Lovers – 20. TLM 1

UVM supports ports (TLM 1) and sockets (TLM 2) as transaction-level interfaces. This post will explain TLM 1. TLM 1 seems daunting as it has many ports, exports, and “imp”s, but once you understand the basics, TLM 1 is not too difficult.

## Ports

Ports define which access methods to use. There are twenty-three port classes in TLM 1. Each port is a subclass of the uvm_port_base class, which in turn is a subclass of the uvm_tlm_if_base class (or a subclass of the uvm_sqr_if_base class in case of the uvm_seq_item_pull_port). See the class diagram below.

TLM 1 Port Classes

The uvm_tlm_if_base class and the uvm_sqr_if_base class define the access methods of a port. By default, each method issues an error message if it is called. Each port overrides a subset of the access methods as listed below. For example, the uvm_blocking_put_port overrides the put method (only). This means if you call a method other than the put, you will get an error message defined in the uvm_tlm_if_base class.

Class \ Methodputtry_ putcan_ putgettry_ getcan_ getpeektry_ peekcan_ peektransportnb_ transportwrite
uvm_blocking_ put_portX
uvm_nonblocking_ put_port XX
uvm_put_portXXX
uvm_blocking_ get_port   X
uvm_nonblocking_ get_port    XX
uvm_get_port   XXX
uvm_blocking_ peek_port      X
uvm_nonblocking_ peek_port       XX
uvm_peek_port      XXX
uvm_blocking_ get_peek_port   X  X
uvm_nonblocking_ get_peek_port    XX XX
uvm_get_peek_port   XXXXXX
uvm_blocking_ master_portX  X  X
uvm_nonblocking_ master_port XX XX XX
uvm_master_portXXXXXXXXX
uvm_blocking_ slave_portX  X  X
uvm_nonblocking_ slave_port XX XX XX
uvm_slave_portXXXXXXXXX
uvm_blocking_ transport_port         X
uvm_nonblocking_ transport_port          X
uvm_transport_port         XX
uvm_analysis_port           X

## Exports

Exports are used when you promote imps (see the next section) to a parent component. Similar to the ports, each export is a subclass of the uvm_port_base class, which in turn is a subclass of the uvm_tlm_if_base class (or a subclass of the uvm_sqr_if_base class in case of the uvm_seq_item_pull_export). See the class diagram below.

TLM 1 Export Classes

Similar to a port class, each export class supports a subset of the access methods. See the corresponding port in the table above to figure out which methods are supported.

## Imps

Imps provide the implementation of access methods. To be precise, the imps delegate the implementation to the component that actually implements the access methods. The type of the component is passed as a parameter when an imp is instantiated. Similar to the ports and exports, each imp is a subclass of the uvm_port_base class, which in turn is a subclass of uvm_tlm_if_base class (or a subclass of the uvm_sqr_if_base class in case of the uvm_seq_item_pull_imp). See the class diagram below.

TLM 1 Imp Classes

Similar to a port class, each imp class supports a subset of the access methods. See the corresponding port in the table above to figure out which methods are supported.

## FIFOs

TLM 1 defines two FIFOs; the uvm_tlm_fifo and the uvm_tlm_analysis_fifo. See the component figure and the class diagram below.

TLM 1 FIFO Components

TLM 1 FIFO Class Diagram

## Channels

TLM 1 defines two channels; the uvm_tlm_req_rsp_channel and the uvm_tlm_transport_channel. See the component figure and the class diagram below.

TLM 1 Channel Components

TLM 1 Channel Class Diagram

The next post will give you an example of how to use the TLM 1 classes.

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