我也要用- 博客(7)
- 资源 (16)
- 收藏
- 关注
RSS订阅翻译 UVM Tutorial for Candy Lovers – 19. Analysis FIFO
This post will explain how to use analysis FIFOs.Let’s assume I wanted a scoreboard that compares two streams of jelly beans; one stream is for “expected” jelly beans, the other is for “actual” jelly...
2020-01-05 15:02:59
120
翻译 UVM Tutorial for Candy Lovers – 18. Configuration Database Revisited
In the post,Configurations, we looked at the configuration flow of the jelly bean verification. We also looked at the behind the scenes of the configuration flow in the post,Configuration Database. ...
2020-01-05 15:01:56
92
翻译 UVM Tutorial for Candy Lovers – 17. Register Read Demystified
In the last post,Register Access Methods, we looked at the primary methods of RAL and showed how they worked. This post will further focus on theread()method and show how the method actually reads ...
2020-01-05 14:58:24
73
翻译 UVM Tutorial for Candy Lovers – 16. Register Access Methods
assert( flavor.randomize() );The register abstraction layer (RAL) of UVM provides several methods to access registers. This post will explain how the register-access methods work.InRegister Abstr...
2020-01-05 14:54:57
112
翻译 UVM Tutorial for Candy Lovers – 15. “Do” Hooks
This post will explain user-definabledo_*hook functions.InField Macros, we saw that the standard data methods, such ascopy()andcompare(), called the user-definable hook functions, such asdo_co...
2020-01-05 14:36:03
96
翻译 UVM Tutorial for Candy Lovers – 14. Field Macros
This post will explain how UVM field macros (`uvm_field_*) work.InTransactions and Sequences, we used the UVM field macros to automatically implement the standard data methods, such ascopy(),compa...
2020-01-05 14:30:53
128
翻译 UVM Tutorial for Candy Lovers – 13. Configuration Database
This post will explain how configuration database (uvm_config_db) works.InConfigurations, we used theuvm_config_dbto store ajelly_bean_if, ajelly_bean_env_config, and twojelly_bean_agent_config...
2020-01-05 14:28:11
127
systemVerilog Assertion应用指南完整版
2018-08-14
ESL Design and Verification.pdf
2019-05-17
SVA_ The Power of Assertions in SystemVerilog
2018-12-26
SystemVerilog Assertions and Functional Coverage_ Guide to Language
2018-12-26
空空如也
空空如也
TA创建的收藏夹 TA关注的收藏夹
TA关注的人 TA的粉丝