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RSS订阅翻译 UVM Tutorial for Candy Lovers – 25. Using a C-Model
We often use a C-model as a reference model. Thanks to the direct programming interface (DPI) of SystemVerilog, using C-model has never been easier. We will show you how to use a C-model in our jelly ...
2020-02-23 11:27:11
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翻译 UVM Tutorial for Candy Lovers – 24. Register Access through the Back Door
This post will add back-door access to the registers defined inRegister Abstraction. With a few additional lines of code, you can access the registers through the back door.DUTWe use the same DUT...
2020-02-23 11:25:16
105
翻译 UVM Tutorial for Candy Lovers – 23. Jelly Bean Taster in UVM 1.2
My first series of UVM tutorials (#1 to #6) was posted more than three years ago. Since then, UVM (and my knowledge about it) has evolved and I always wanted to update my articles and code. But it was...
2020-02-23 11:18:40
165
翻译 UVM Tutorial for Candy Lovers – 22. Phasing
When we created thejelly_bean_driverinAgent, we coded thebuild_phasefunction and therun_phasetask, but who actually calls them? The answer isuvm_phaseclass.UVM PhasesUVM has nine common p...
2020-02-23 11:15:04
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翻译 UVM Tutorial for Candy Lovers – 21. TLM 1 Example
In theprevious post, we looked at an overview of the TLM 1 classes. This post will give you a sample code using some of the TLM 1 classes.ComponentsWe created the following components to demonstr...
2020-02-23 11:12:36
114
翻译 UVM Tutorial for Candy Lovers – 20. TLM 1
UVM supports ports (TLM 1) and sockets (TLM 2) as transaction-level interfaces. This post will explain TLM 1.TLM 1 seems daunting as it has many ports, exports, and “imp”s, but once you understand th...
2020-02-23 11:07:37
103
systemVerilog Assertion应用指南完整版
2018-08-14
ESL Design and Verification.pdf
2019-05-17
SVA_ The Power of Assertions in SystemVerilog
2018-12-26
SystemVerilog Assertions and Functional Coverage_ Guide to Language
2018-12-26
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