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TroubleMaker

为天地立心,为生民立命,为往圣继绝学,为万世开太平

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翻译 UVM Tutorial for Candy Lovers – 25. Using a C-Model

We often use a C-model as a reference model. Thanks to the direct programming interface (DPI) of SystemVerilog, using C-model has never been easier. We will show you how to use a C-model in our jelly ...

2020-02-23 11:27:11 90

翻译 UVM Tutorial for Candy Lovers – 24. Register Access through the Back Door

This post will add back-door access to the registers defined inRegister Abstraction. With a few additional lines of code, you can access the registers through the back door.DUTWe use the same DUT...

2020-02-23 11:25:16 105

翻译 UVM Tutorial for Candy Lovers – 23. Jelly Bean Taster in UVM 1.2

My first series of UVM tutorials (#1 to #6) was posted more than three years ago. Since then, UVM (and my knowledge about it) has evolved and I always wanted to update my articles and code. But it was...

2020-02-23 11:18:40 165

翻译 UVM Tutorial for Candy Lovers – 22. Phasing

When we created thejelly_bean_driverinAgent, we coded thebuild_phasefunction and therun_phasetask, but who actually calls them? The answer isuvm_phaseclass.UVM PhasesUVM has nine common p...

2020-02-23 11:15:04 84

翻译 UVM Tutorial for Candy Lovers – 21. TLM 1 Example

In theprevious post, we looked at an overview of the TLM 1 classes. This post will give you a sample code using some of the TLM 1 classes.ComponentsWe created the following components to demonstr...

2020-02-23 11:12:36 114

翻译 UVM Tutorial for Candy Lovers – 20. TLM 1

UVM supports ports (TLM 1) and sockets (TLM 2) as transaction-level interfaces. This post will explain TLM 1.TLM 1 seems daunting as it has many ports, exports, and “imp”s, but once you understand th...

2020-02-23 11:07:37 103

systemVerilog Assertion应用指南完整版

systemVerilog Assertion应用指南完整版。网上流传的其他版本都不是完整的,这次终于找到了完整的版本,分享给大家。

2018-08-14

AMBA_UVM验证DEMO

AMBA_UVM验证,可以在VCS等仿真工具中进行运行,可以帮助你更好的理解UVM验证平台

2019-01-29

电子技术基础:数字部分

benPPT是电子技术基础:数字部分的内容,有兴趣的朋友可以查看。

2019-04-09

APB_SPI_master

本文件可以作为有需求的在校生学习使用,有完整的程序代码。

2018-08-14

sv_lab.zip

一个demo,关于systemverilog,完成的design和verification。希望有需要的朋友能看到

2019-10-16

uvm_lab.zip

一个demo,关于UVM,完成的design和verification。希望有需要的朋友能看到

2019-10-16

ESL Design and Verification.pdf

ESL Design and Verification: A Prescription for Electronic System Level Methodology

2019-05-17

uvm-cookbook-complete-verification-academy

uvm-cookbook-complete-verification-academy

2019-01-02

SVA_ The Power of Assertions in SystemVerilog

Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny (auth.) - SVA_ The Power of Assertions in SystemVerilog-Springer International Publishing (2015)

2018-12-26

SystemVerilog Assertions and Functional Coverage_ Guide to Language

Ashok B. Mehta (auth.) - SystemVerilog Assertions and Functional Coverage_ Guide to Language, Methodology and Applications-Springer International Publishing (2016)

2018-12-26

高级项目管理师-项目风险管理论文

高级项目管理师-项目风险管理论文。

2018-11-11

算法之道_第二版全目录

算法之道,事关算法。有兴趣的朋友可以阅读下载。谢谢!

2018-11-04

SD_part1_Physical_Layer_spec

SD_part1_Physical_Layer_spec. SD协议_物理层标准 有兴趣可以一起学习

2018-10-18

AMBA_AHB_DMA

本文件为Verilog文件,适合研习AMBA总线的朋友学习使用。

2018-08-17

AMBA_APB_I2C

本文件为Verilog文件,适合研习AMBA总线的朋友学习使用。

2018-08-15

Intermediate PERL

Intermediate PERL.

2018-08-14

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